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| 8 Bit Microcontroller TLCS-870/C Series TMP86CS28FG The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2006/12/5 2006/12/14 2007/7/21 Revision 1 2 3 First Release Contents Revised Contents Revised Table of Contents TMP86CS28FG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map............................................................................................................................... 9 Program Memory (MaskROM).................................................................................................................. 9 Data Memory (RAM) ................................................................................................................................. 9 Clock Generator...................................................................................................................................... 10 Timing Generator .................................................................................................................................... 12 Operation Mode Control Circuit .............................................................................................................. 13 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 18 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset Input ............................................................................................................................... Address trap reset .................................................................................................................................. Watchdog timer reset.............................................................................................................................. System clock reset.................................................................................................................................. 31 32 32 32 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 Interrupt latches (IL30 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt master enable flag (IMF) .......................................................................................................... 36 Individual interrupt enable flags (EF30 to EF4) ...................................................................................... 37 Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 Interrupt acceptance processing is packaged as follows........................................................................ 39 Saving/restoring general-purpose registers ............................................................................................ 40 Interrupt return ........................................................................................................................................ 41 Using PUSH and POP instructions Using data transfer instructions 3.3.2.1 3.3.2.2 3.2.1 3.2.2 3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address error detection .......................................................................................................................... 42 Debugging .............................................................................................................................................. 42 i 3.5 3.6 3.7 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Port P0 (P00 to P02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P10 to P17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P20 to P22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P30 to P37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P40 to P47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P50 to P57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P60 to P67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P70 to P77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P8 (P80 to P87) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 55 58 59 61 63 65 67 69 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 72 73 74 74 75 6.3 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 76 76 76 77 6.3.1 6.3.2 6.3.3 6.3.4 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Configuration .......................................................................................................................................... 79 Control .................................................................................................................................................... 79 Function .................................................................................................................................................. 80 Configuration .......................................................................................................................................... 81 Control .................................................................................................................................................... 81 7.1.1 7.1.2 7.1.3 7.2.1 7.2.2 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ii 8.1.1 8.1.2 8.1.3 Configuration .......................................................................................................................................... 83 TimerCounter Control ............................................................................................................................. 84 Function .................................................................................................................................................. 85 Timer mode External Trigger Timer Mode Event Counter Mode Window Mode Pulse Width Measurement Mode Programmable Pulse Generate (PPG) Output Mode 8.2 8.1.3.1 8.1.3.2 8.1.3.3 8.1.3.4 8.1.3.5 8.1.3.6 16-Bit TimerCounter 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Configuration .......................................................................................................................................... 97 TimerCounter Control ............................................................................................................................. 98 Function .................................................................................................................................................. 99 Timer mode External Trigger Timer Mode Event Counter Mode Window Mode Pulse Width Measurement Mode Programmable Pulse Generate (PPG) Output Mode 8.2.1 8.2.2 8.2.3 8.2.3.1 8.2.3.2 8.2.3.3 8.2.3.4 8.2.3.5 8.2.3.6 9. 8-Bit TimerCounter (TC3, TC4) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8-Bit Timer Mode (TC3 and 4) .............................................................................................................. 8-Bit Event Counter Mode (TC3, 4) ...................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)................................................................ 16-Bit Timer Mode (TC3 and 4) ............................................................................................................ 16-Bit Event Counter Mode (TC3 and 4) .............................................................................................. 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)........................................................ 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................. Warm-Up Counter Mode....................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 117 118 118 121 123 124 124 127 129 9.3.9.1 9.3.9.2 10. 8-Bit TimerCounter (TC5, TC6) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 8-Bit Event Counter Mode (TC5, 6) .................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)................................................................. 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).............................................................. 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 16-Bit Event Counter Mode (TC5 and 6) ............................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... Warm-Up Counter Mode..................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 137 138 138 141 143 144 144 147 149 10.3.9.1 10.3.9.2 11. Synchronous Serial Interface (SIO) 11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 iii 11.2 11.3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Clock source ....................................................................................................................................... 153 Shift edge............................................................................................................................................ 155 Leading edge Trailing edge Internal clock External clock 11.3.1.1 11.3.1.2 11.3.2.1 11.3.2.2 11.3.1 11.3.2 11.4 11.5 11.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4-bit and 8-bit transfer modes ............................................................................................................. 156 4-bit and 8-bit receive modes ............................................................................................................. 158 8-bit transfer / receive mode ............................................................................................................... 159 11.6.1 11.6.2 11.6.3 12. Asynchronous Serial interface (UART1 ) 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 166 Data Receive Operation ..................................................................................................................... 166 167 167 167 168 168 169 161 162 164 165 165 166 166 166 12.8.1 12.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 13. Asynchronous Serial interface (UART0 ) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 176 Data Receive Operation ..................................................................................................................... 176 177 177 177 178 178 179 171 172 174 175 175 176 176 176 13.8.1 13.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 13.9.1 13.9.2 13.9.3 13.9.4 13.9.5 13.9.6 iv 14. 10-bit AD Converter (ADC) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Software Start Mode ........................................................................................................................... 185 Repeat Mode ...................................................................................................................................... 185 Register Setting ................................................................................................................................ 186 14.4 14.5 14.6 14.3.1 14.3.2 14.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 188 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Analog input pin voltage range ........................................................................................................... 189 Analog input shared pins .................................................................................................................... 189 Noise Countermeasure ....................................................................................................................... 189 14.6.1 14.6.2 14.6.3 15. Key-on Wakeup (KWU) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 16. LCD Driver 16.1 16.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 LCD driving methods .......................................................................................................................... 195 Frame frequency................................................................................................................................. 196 Driving method for LCD driver ............................................................................................................ 197 When using the booster circuit (LCDCR 16.2.1 16.2.2 16.2.3 16.3 16.4 16.2.3.1 16.2.3.2 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Initial setting ........................................................................................................................................ 201 Store of display data ........................................................................................................................... 201 Example of LCD drive output .............................................................................................................. 204 Display data setting ............................................................................................................................ 199 Blanking .............................................................................................................................................. 200 16.3.1 16.3.2 16.4.1 16.4.2 16.4.3 17. Input/Output Circuitry 17.1 17.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 18. Electrical Characteristics 18.1 18.2 18.3 18.4 18.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ............................................................................................................................................................... 212 v 18.5 18.6 18.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 19. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vi TMP86CS28FG CMOS 8-Bit Microcontroller TMP86CS28FG Product No. TMP86CS28FG ROM (MaskROM) 61440 bytes RAM 2048 bytes Package QFP80-P-1420-0.80B FLASH MCU TMP86FS28FG Emulation Chip TMP86C989XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 23interrupt sources (External : 6 Internal : 17) 3. Input / Output ports (62 pins) 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 16-bit timer counter: 2 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. 8-bit UART/SIO: 1 ch 9. 8-bit UART : 1 ch * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CS28FG 10. 10-bit successive approximation type AD converter - Analog input: 8 ch 11. Key-on wakeup : 4 ch 12. LCD driver/controller Built-in voltage booster for LCD driver With display memory LCD direct drive capability (MAX 40 seg x 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable 13. Clock operation Single clock mode Dual clock mode 14. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 2.7 V to 5.5 V at 8MHz /32.768 kHz 4.0 V to 5.5 V at 16 MHz /32.768 kHz Release by Page 2 1.2 Pin Assignment (SEG6) P81 (SEG5) P82 (SEG4) P83 (SEG3) P84 (SEG2) P85 (SEG1) P86 (SEG0) P87 COM3 COM2 COM1 COM0 V3 V2 V1 C1 C0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (INT5/STOP) P20 P00 P01 (INT3/PPG10) P02 AVDD VAREF (AIN0) P10 (AIN1) P11 (STOP2/AIN2) P12 (STOP3/AIN3) P13 (STOP4/AIN4) P14 (STOP5/AIN5) P15 (AIN6) P16 (AIN7) P17 AVSS (INT0) P30 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P80 (SEG7) P77 (SEG8) P76 (SEG9) P75 (SEG10) P74 (SEG11) P73 (SEG12) P72 (SEG13) P71 (SEG14) P70 (SEG15) P67 (SEG16) P66 (SEG17) P65 (SEG18) P64 (SEG19) P63 (SEG20) P62 (SEG21) P61 (SEG22) P60 (SEG23) P57 (SEG24) P56 (SEG25) P55 (SEG26/TC6/PDO6/PWM6/PPG6) P54 (SEG27/TC5/PDO5/PWM5) P53 (SEG28/TC4/PDO4/PWM4/PPG4) P52 (SEG29/TC3/PDO3/PWM3) P51 (SEG30/RXD0) P50 (SEG31/TXD0) P47 (SEG32) P46 (SEG33) P45 (SEG34) P44 (SEG35) P43 (SEG36/TC11) P42 (SEG37/PPG11) P41 (SEG38/INT2) P40 (SEG39/INT1) P37 (TC10/INT4) P36(SCK) P35(SI/TXD1) P34(SO/RXD1) P33 P32 P31(DVO) TMP86CS28FG 1.3 Block Diagram TMP86CS28FG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CS28FG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/4) Pin Name P02 PPG10 Pin Number Input/Output IO O I IO IO IO I IO I IO I I IO I I IO I I IO I I IO I IO I IO O PORT02 PPG10 output External interrupt 3 input PORT01 PORT00 PORT17 Analog Input7 PORT16 Analog Input6 PORT15 Analog Input5 STOP5 input PORT14 Analog Input4 STOP4 input PORT13 Analog Input3 STOP3 input PORT12 Analog Input2 STOP2 input PORT11 Analog Input1 PORT10 Analog Input0 Functions 12 INT3 P01 P00 P17 AIN7 P16 AIN6 P15 AIN5 STOP5 P14 AIN4 STOP4 P13 AIN3 STOP3 P12 AIN2 STOP2 P11 AIN1 P10 AIN0 P22 XTOUT 11 10 22 21 20 19 18 17 16 15 7 PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 STOP mode release signal input External interrupt 5 input PORT37 TC10 input External interrupt 4 input PORT36 Serial Clock I/O PORT35 Serial Data Input UART data output 1 PORT34 Serial Data Output UART data input 1 PORT33 P21 XTIN P20 STOP INT5 6 IO I IO I I IO I I IO IO IO I O IO O I IO 9 P37 TC10 INT4 P36 SCK 31 30 P35 SI TXD1 P34 SO RXD1 P33 29 28 27 Page 5 1.4 Pin Names and Functions TMP86CS28FG Table 1-1 Pin Names and Functions(2/4) Pin Name P32 P31 DVO Pin Number 26 25 Input/Output IO IO O IO I IO O IO O IO O IO O IO O I IO O O IO O I IO O I IO O IO O IO O I O IO O I O IO O I O IO O I O IO O I IO O O PORT32 PORT31 Divider Output PORT30 External interrupt 0 input PORT47 LCD segment output 32 PORT46 LCD segment output 33 PORT45 LCD segment output 34 PORT44 LCD segment output 35 PORT43 LCD segment output 36 TC11 input PORT42 LCD segment output 37 PPG11 output PORT41 LCD segment output 38 External interrupt 2 input PORT40 LCD segment output 39 External interrupt 1 input PORT57 LCD segment output 24 PORT56 LCD segment output 25 Functions P30 INT0 24 P47 SEG32 P46 SEG33 P45 SEG34 P44 SEG35 P43 SEG36 TC11 P42 SEG37 PPG11 39 38 37 36 35 34 P41 SEG38 INT2 P40 SEG39 INT1 P57 SEG24 P56 SEG25 P55 SEG26 TC6 PDO6/PWM6/PPG6 33 32 47 46 45 PORT55 LCD segment output 26 TC6 input PDO6/PWM6/PPG6 output PORT54 LCD segment output 27 TC5 input PDO5/PWM5 output PORT53 LCD segment output 28 TC4 input PDO4/PWM4/PPG4 output PORT52 LCD segment output 29 TC3 input PORT51 LCD segment output 30 UART data input 0 PORT50 LCD segment output 31 UART data output 0 P54 SEG27 TC5 PDO5/PWM5 44 P53 SEG28 TC4 PDO4/PWM4/PPG4 43 P52 SEG29 TC3 PDO3/PWM3 42 P51 SEG30 RXD0 P50 SEG31 TXD0 41 40 Page 6 TMP86CS28FG Table 1-1 Pin Names and Functions(3/4) Pin Name P67 SEG16 P66 SEG17 P65 SEG18 P64 SEG19 P63 SEG20 P62 SEG21 P61 SEG22 P60 SEG23 P77 SEG8 P76 SEG9 P75 SEG10 P74 SEG11 P73 SEG12 P72 SEG13 P71 SEG14 P70 SEG15 P87 SEG0 P86 SEG1 P85 SEG2 P84 SEG3 P83 SEG4 P82 SEG5 P81 SEG6 Pin Number 55 Input/Output IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O PORT67 LCD segment output 16 PORT66 LCD segment output 17 PORT65 LCD segment output 18 PORT64 LCD segment output 19 PORT63 LCD segment output 20 PORT62 LCD segment output 21 PORT61 LCD segment output 22 PORT60 LCD segment output 23 PORT77 LCD segment output 8 PORT76 LCD segment output 9 PORT75 LCD segment output 10 PORT74 LCD segment output 11 PORT73 LCD segment output 12 PORT72 LCD segment output 13 PORT71 LCD segment output 14 PORT70 LCD segment output 15 PORT87 LCD segment output 0 PORT86 LCD segment output 1 PORT85 LCD segment output 2 PORT84 LCD segment output 3 PORT83 LCD segment output 4 PORT82 LCD segment output 5 PORT81 LCD segment output 6 Functions 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56 71 70 69 68 67 66 65 Page 7 1.4 Pin Names and Functions TMP86CS28FG Table 1-1 Pin Names and Functions(4/4) Pin Name P80 SEG7 COM3 COM2 COM1 COM0 V3 V2 V1 C1 C0 XIN XOUT RESET Pin Number 64 72 73 74 75 76 77 78 79 80 2 3 8 4 14 13 23 5 1 Input/Output IO O O O O O I I I I I I O I I I I I I I PORT80 LCD segment output 7 LCD common output 3 LCD common output 2 LCD common output 1 LCD common output 0 LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin Functions Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply Analog Power Supply Power Supply 0(GND) TEST VAREF AVDD AVSS VDD VSS Page 8 TMP86CS28FG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CS28FG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the memory address map. TMP86CS28FG 0000H SFR 003FH 0040H 64 bytes SFR: RAM 083FH 0F00H 2048 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack DBR: DBR 0FFFH 1000H 256 bytes MaskROM: Data buffer register includes: Peripheral control registers Peripheral status registers LCD display memory Program memory MaskROM FFA0H FFBFH FFC0H FFDFH FFE0H FFFFH 61440 bytes Vector table for interrupts (32 bytes) Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CS28FG has a 61440 bytes (Address 1000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86CS28FG has 2048 bytes (Address 0040H to 083FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. Page 9 2. Operational Description 2.2 System Clock Controller TMP86CS28FG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86CS28FG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 07FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86CS28FG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller TMP86CS28FG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 7. LCD 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86CS28FG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CS28FG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CS28FG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 14 TMP86CS28FG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86CS28FG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 16 TMP86CS28FG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 17 2. Operational Description 2.2 System Clock Controller TMP86CS28FG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 18 TMP86CS28FG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86CS28FG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 21 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CS28FG 2. Operational Description 2.2 System Clock Controller TMP86CS28FG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Yes "0" IMF Reset Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86CS28FG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86CS28FG (b) IDLE1/2 and SLEEP1/2 modes release TMP86CS28FG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86CS28FG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF6*TBTCR (2) Interrupt release mode (IMF*EF6*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 26 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86CS28FG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86CS28FG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC4: CLR SET (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 28 TMP86CS28FG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC4: CLR CLR (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 29 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CS28FG SLOW1 mode NORMAL2 mode TMP86CS28FG 2.3 Reset Circuit The TMP86CS28FG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 LCD data buffer RAM Refer to each of control register Not initialized Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86CS28FG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 32 TMP86CS28FG Page 33 2. Operational Description 2.3 Reset Circuit TMP86CS28FG Page 34 TMP86CS28FG 3. Interrupt Control Circuit The TMP86CS28FG has a total of 23 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 IL30 IL31 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 FFE6 FFE4 FFE2 FFE0 FFBE FFBC FFBA FFB8 FFB6 FFB4 FFB2 FFB0 FFAE FFAC FFAA FFA8 FFA6 FFA4 FFA2 FFA0 Interrupt Factors Internal/External Internal Internal Internal Internal External External Internal Internal Internal Internal Internal External Internal Internal Internal External Internal Internal External External Internal Internal Internal (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1 IMF* EF15 = 1 IMF* EF16 = 1 IMF* EF17 = 1 IMF* EF18 = 1 IMF* EF19 = 1 IMF* EF20 = 1 IMF* EF21 = 1 IMF* EF22 = 1 IMF* EF23 = 1 IMF* EF24 = 1 IMF* EF25 = 1 IMF* EF26 = 1 IMF* EF27 = 1 IMF* EF28 = 1 IMF* EF29 = 1 IMF* EF30 = 1 IMF* EF31 = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INT1 INTTBT INTTC10 INTRXD0 INTTXD0 INTTC11 INT2 Reserved INTSIO Reserved Reserved Reserved Reserved Reserved Reserved INTTC3 INTTC4 INT3 INTTC5 INTTC6 INT4 INT5 INTRXD1 INTTXD1 INTADC Reserved Reserved Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1 Page 35 3. Interrupt Control Circuit 3.1 Interrupt latches (IL30 to IL2) TMP86CS28FG 3.1 Interrupt latches (IL30 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 002EH, 002FH, 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modifywrite instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 002CH, 002DH, 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". Page 36 TMP86CS28FG 3.2.2 Individual interrupt enable flags (EF30 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF30 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CS28FG Interrupt Latches (Initial value: **0*0000 000000**) ILH,ILL (003DH, 003CH) 15 - 14 - 13 IL13 12 - 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) (Initial value: **000000 0000****) ILD,ILE (002FH, 002EH) 15 - 14 - 13 IL29 12 IL28 11 IL27 10 IL26 9 IL25 8 IL24 7 IL23 6 IL22 5 IL21 4 IL20 3 - 2 - 1 - 0 - ILD (002FH) ILE (002EH) IL30 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: **0*0000 0000***0) EIRH,EIRL (003BH, 003AH) 15 - 14 - 13 EF13 12 - 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) (Initial value: **000000 0000****) EIRD,EIRE (002DH, 002CH) 15 - 14 - 13 EF29 12 EF28 11 EF27 10 EF26 9 EF25 8 EF24 7 EF23 6 EF22 5 EF21 4 EF20 3 - 2 - 1 - 0 - EIRD (002DH) EIRE (002CH) EF30 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86CS28FG 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF2H FFF3H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address Page 39 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP86CS28FG A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. 3.3.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.3.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Page 40 TMP86CS28FG Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Page 41 3. Interrupt Control Circuit 3.4 Software Interrupt (INTSW) TMP86CS28FG Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.4.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.4.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.5 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.6 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). Page 42 TMP86CS28FG 3.7 External Interrupts The TMP86CS28FG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P30 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P30 pin function selection are performed by the external interrupt control register (EINTCR). Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT2 INT2 IMF EF11 = 1 Falling edge or Rising edge INT3 INT3 IMF EF22 = 1 Falling edge or Rising edge INT4 INT4 IMF EF25 = 1 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF26 = 1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 43 3. Interrupt Control Circuit 3.7 External Interrupts TMP86CS28FG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC INT0EN Noise reject time select P30/INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P30 input/output port 1: INT0 pin (Port P30 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W INT4 ES INT4 edge select R/W INT3 ES INT2 ES INT1 ES INT3 edge select INT2 edge select INT1 edge select R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 44 TMP86CS28FG 4. Special Function Register (SFR) The TMP86CS28FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F00H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86CS28FG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H Read P0DR P1DR P2DR P3DR P4DR P5DR P6DR P7DR P8DR TC3CR TC4CR TC5CR TC6CR Reserved Reserved Reserved TC10DRAL TC10DRAH TC10DRBL TC10DRBH TC10CR TTREG3 TTREG4 TTREG5 TTREG6 PWREG3 PWREG4 PWREG5 PWREG6 Reserved Reserved Reserved TC11DRAL TC11DRAH TC11DRBL TC11DRBH TC11CR Reserved Write Page 45 4. Special Function Register (SFR) 4.1 SFR TMP86CS28FG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read Reserved Reserved Reserved Reserved Reserved P3OUTCR EIRE EIRD ILE ILD Reserved P0OUTCR Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH Reserved PSW Write STOPCR WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 46 TMP86CS28FG 4.2 DBR Address 0F00H :: 0F5FH Read Reserved :: Reserved Write Address 0F60H 0F61H 0F62H 0F63H 0F64H 0F65H 0F66H 0F67H 0F68H 0F69H Read SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 SIOSR Write SIOCR1 SIOCR2 Address 0F70H :: 0F7FH Read Reserved :: Reserved Write Page 47 4. Special Function Register (SFR) 4.2 DBR TMP86CS28FG Address 0F80H :: 0F9FH Read Reserved :: Reserved Write Address 0FA0H :: 0FBFH Read Reserved :: Reserved Write Address 0FC0H 0FC1H 0FC2H 0FC3H 0FC4H 0FC5H 0FC6H 0FC7H 0FC8H 0FC9H 0FCAH 0FCBH 0FCCH 0FCDH 0FCEH 0FCFH 0FD0H 0FD1H 0FD2H 0FD3H 0FD4H 0FD5H 0FD6H 0FD7H 0FD8H 0FD9H 0FDAH 0FDBH 0FDCH 0FDDH 0FDEH 0FDFH Read SEG1/0 SEG3/2 SEG5/4 SEG7/6 SEG9/8 SEG11/10 SEG13/12 SEG15/14 SEG17/16 SEG19/18 SEG21/20 SEG23/22 SEG25/24 SEG27/26 SEG29/28 SEG31/30 SEG33/32 SEG35/34 SEG37/36 SEG39/38 P4LCR P5LCR P6LCR P7LCR P8LCR LCDCR Reserved Reserved Reserved Reserved Reserved Reserved Write Page 48 TMP86CS28FG Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H 0FF6H 0FF7H 0FF8H 0FF9H 0FFAH 0FFBH 0FFCH 0FFDH 0FFEH 0FFFH Read ADCDR2 ADCDR1 ADCCR1 ADCCR2 Reserved UART0SR RD0BUF UART1SR RD1BUF Reserved Reserved Reserved Reserved Reserved P0PRD Reserved P2PRD P3PRD P4PRD P5PRD P6PRD P7PRD P8PRD P1CR1 P1CR2 P4OUTCR P5OUTCR P6OUTCR P7OUTCR P8OUTCR Write - UART0CR1 UART0CR2 TD0BUF UART1CR1 UART1CR2 TD1BUF - - Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 49 4. Special Function Register (SFR) 4.2 DBR TMP86CS28FG Page 50 TMP86CS28FG 5. I/O Ports The TMP86CS28FG has 9 input/output ports (62 pins) as shown below. Table 5-1 Port Functions Primary Function Port P0 Port P1 Port P2 3-bit input/output port 8-bit input/output port 3-bit input/output port Secondary Functions External interrupt input, PPG output Analog input, STOP mode release signal input External interrupt input, low-frequency resonator connection, STOP mode release signal input External interrupt input, timer/counter input, serial interface input/output, UART input/output, divider output External interrupt input, timer/counter input, LCD segment output, PPG output Timer/counter input/output, LCD segment output, UART input/output LCD segment output LCD segment output LCD segment output Port P3 Port P4 Port P5 Port P6 Port P7 Port P8 8-bit input/output port 8-bit input/output port 8-bit input/output port 8-bit input/output port 8-bit input/output port 8-bit input/output port Table 5-2 Port P0 P1 P2 P3 P4 P5 P6 P7 P8 Register List Read P0PRD (0FF0H) - P2PRD (0FF2H) P3PRD (0FF3H) P4PRD (0FF4H) P5PRD (0FF5H) P6PRD (0FF6H) P7PRD (0FF7H) P8PRD (0FF8H) Pch Control P0OUTCR (0032H) - - P3OUTCR (002BH) P4OUTCR (0FFBH) P5OUTCR (0FFCH) P6OUTCR (0FFDH) P7OUTCR (0FFEH) P8OUTCR (0FFFH) CR1 - P1CR1 (0FF9H) - - - - - - - CR2 - P1CR2 (0FFAH) - - - - - - - LCD Control - - - - P4LCR (0FD4H) P5LCR (0FD5H) P6LCR (0FD6H) P7LCR (0FD7H) P8LCR (0FD8H) P0DR (0000H) Latch P1DR (0001H) P2DR (0002H) P3DR (0003H) P4DR (0004H) P5DR (0005H) P6DR (0006H) P7DR (0007H) P8DR (0008H) Page 51 5. I/O Ports TMP86CS28FG Each output port contains a latch for holding output data. All input ports do not have latches, making it necessary to externally hold input data until it is read externally or to read input data multiple times before it is processed. Figure 5-1 shows input/output timings. External data is read from an input/output port in the S1 state of the read cycle in instruction execution. Since this timing cannot be recognized externally, transient input such as chattering must be processed by software. Data is output to an input/output port in the S2 state of the write cycle in instruction execution. Fetch cycle Instruction execution cycle Input strobe Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD A, (x) Data input (a) Input timing Fetch cycle Instruction execution cycle Output latch pulse Fetch cycle Write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Ex: LD (x), A Data output (b) Output timing Note: The positions of the read and write cycles may vary depending on the instruction. Figure 5-1 Input/Output Timings (Example) Page 52 TMP86CS28FG 5.1 Port P0 (P00 to P02) Port P0 is a 3-bit input/output port that can also be used for external interrupt input or PPG output. A reset initializes the output latch (P0DR) to "1" and the Pch control (P0OUTCR) to "0". To use a pin in Port P0 as an input port or external interrupt input, set P0DR to "1" and then set the corresponding bit in P0OUTCR to "0". To use a pin in Port P0 as a PPG output, set P0DR to "1". The output circuit of Port P0 can be set either as sink open-drain output ("0") or CMOS output ("1") individually for each bit in P0OUTCR. Port P0 has a separate data input register. The output latch state can be read from the P0DR register, and the pin state can be read from the P0PRD register. Table 5-3 Register Programming for Port P0 (P00 to P02) Programmed Value Function P0DR Port input, external interrupt input Port "0" output Port "1" output, PPG output "1" "0" "1" P0OUTCR "0" Set as appropriate. STOP OUTEN P0OUTCRi P0OUTCRi input Data input (P0PRD) Output latch read (P0DR) Data output (P0DR) Control output Control input D Q P0i Note) i = 2~0 D Q Output latch Figure 5-2 Port P0 Page 53 5. I/O Ports 5.1 Port P0 (P00 to P02) TMP86CS28FG P0DR (0000H) R/W P0OUTCR (0032H) R/W 7 6 5 4 3 2 P02 PPG1 1 P01 0 P00 (Initial value: **** *111) INT3 7 6 5 4 3 2 1 0 (Initial value: **** *000) P0OUTCR Port P0 input/output control (set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P0PRD (0FF0H) Read only 7 6 5 4 3 2 P02 1 P01 0 P00 (Initial value: **** *000) Page 54 TMP86CS28FG 5.2 Port P1 (P10 to P17) Port P1 is an 8-bit input/output port that can be configured as an input or an output on a bit basis. Port P1 is also used for analog input or key-on wake-up input. The Port P1 input/output control register (P1CR1) and Port P1 input control register (P1CR2) are used to specify the function of each pin. A reset initializes P1CR1 to "0", P1CR2 to "1", and the output latch (P1DR) to "0" so that Port P1 becomes an input port. To use a pin in Port P1 as an input port, set P1CR1 to "0" and then set P1CR2 to "1". To use a pin in Port P1 as an analog input or key-on wake-up input, set P1CR1 to "0" and then set P1CR2 to "0". To use a pin in Port P1 as an output port, set the corresponding bit in P1CR1 to "1". To read the output latch data, set P1CR1 to "1"and read P1DR. To read the pin state, set P1CR1 to "0" and P1CR2 to "1" and then read P1DR. When P1CR1 = "0" and P1CR2 = "0", P1DR is read as "0". Bits not used as analog inputs are used as input/output pins. During AD conversion, however, output instructions must not be executed to ensure the accuracy of conversion results. Also, during AD conversion, do not input signals that fluctuate widely to pins near analog input pins. Table 5-4 Register Programming for Port P1 (P10 to P17) Programmed Value Function P1DR Port input Analog input, key-on wake-up input Port "0" output Port "1" output * * "0" "1" P1CR1 "0" "0" "1" "1" P1CR2 "1" "0" * * Note: An asterisk (*) indicates that either "1" or "0" can be set. Table 5-5 Values Read from P1DR according to Register Programming Conditions Values Read from P1DR P1CR1 "0" "0" "1" "1" P1CR2 "0" "1" "0" Output latch state "0" Pin state Page 55 5. I/O Ports 5.2 Port P1 (P10 to P17) TMP86CS28FG Analog input AINDS SAIN P CR2i P1CR2i input P1CR1i P1CR1i input Data input (P1DR) D Q D Q Data output (P1DR) STOP OUTEN STOPk Key-on wake-up Analog input AINDS SAIN P1CR2j P1CR2j input P1CR1j P1CR1j input Data input (P1DR) D Q P1i Note 1) i = 0, 1, 6, 7 : j = 2~5 : k = 2~5 Note 2) STOP = bit 7 in SYSCR1 Note 3) SAIN = AD input select signal Note 4) STOPk = input select signal for key-on wake-up D Q D Q Data output (P1DR) STOP OUTEN D Q P1j Figure 5-3 Port P1 Note 1: Pins set to input mode read the pin input data. Therefore, when both input and output modes are used in Port P1, the contents of the output latch of a pin set to input mode may be overwritten by a bit manipulation instruction. Note 2: For a pin used as an analog input, be sure to clear the corresponding bit in P1CR2 to "0" to prevent flow-through current. Note 3: For a pin used as an analog input, do not set P1CR1 to "1" (port output) to prevent the pin from becoming shorted with an external signal. Note 4: Pins not used as analog inputs can be used as input/output pins. During AD conversion, however, output instructions must not be executed to ensure the accuracy of conversion results. Also, during AD conversion, do not input signals that fluctuate widely to pins near analog input pins. Page 56 TMP86CS28FG P1DR (0001H) R/W P1CR1 (0FF9H) 7 P17 AIN7 7 6 P16 AIN6 6 5 P15 AIN5 STOP5 5 4 P14 AIN4 STOP4 4 3 P13 AIN3 STOP3 3 2 P12 AIN2 STOP2 2 1 P11 AIN1 1 0 P10 AIN0 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P1CR1 Port P1 input/output control (set for each bit individually) 0: Port input, key-on wake-up input, analog input 1: Port output R/W P1CR2 (0FFAH) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P1CR2 Port P1 input control (set for each bit individually) 0: Analog input, key-on wake-up input 1: Port input R/W Page 57 5. I/O Ports 5.3 Port P2 (P20 to P22) TMP86CS28FG 5.3 Port P2 (P20 to P22) Port P2 is a 3-bit input/output port that can also be used for external interrupt input, STOP mode release signal input, or low-frequency resonator connection. To use Port P2 as an input port or function pins, set the output latch (P2DR) to "1". A reset initializes P2DR to "1". In the dual clock mode, pins P21 (XTIN) and P22 (XOUT) are connected with a low-frequency resonator (32.768 kHz). In the single clock mode, pins P21 and P22 can be used as normal input/output port pins. It is recommended that pin P20 be used as an external interrupt input, STOP release signal input, or input port. (When P20 is used as an output port, the interrupt latch is set on the falling edge of the output pulse.) Port P2 has a separate data input register. The output latch state can be read from the P2DR register, and the pin state can be read from the P2PRD register. When a read instruction is executed on P2DR or P2PRD, bits 7 to 3 are read as undefined. Data input (P20PRD) Data input (P20) Data output (P20) D Q P20 (INT5, STOP) Output latch Control input Data input (P21PRD) Output latch read (P21) Data output (P21) Data input (P22PRD) Output latch read (P22) Data output (P22) D Q P22 (XTOUT) D Q P21 (XTIN) Osc. enable Output latch Output latch STOP OUTEN XTEN fs Figure 5-4 Port P2 P2DR (0002H) R/W P2PRD (0FF2H) Read only 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 1 P21 0 P20 INT5 STOP (Initial value: **** *111) 7 6 5 4 3 2 P22 0 P20 Note: Since pin P20 is also used as a STOP pin, the output of P20 becomes high-impedance in STOP mode regardless of the OUTEN state. Page 58 TMP86CS28FG 5.4 Port P3 (P30 to P37) Port P3 is an 8-bit input/output port that can also be used for external interrupt input, divider output, timer/counter input, serial interface input/output, or UART input/output. A reset initializes the output latch (P3DR) to "1" and the Pch control (P3OUTCR) to "0". To use a pin in Port P3 as an external interrupt input, timer/counter input, serial interface input, or UART input, set P3DR to "1" and then set the corresponding bit in P3OUTCR to "0". To use a pin in Port P3 as a divider output, serial interface output, or UART output, set P3DR to "1". Port 3 can be used for either SIO or UART, so be sure not to enable both of these functions at the same time. The output circuit of Port P3 can be set either as sink open-drain output ("0") or CMOS output ("1") individually for each bit in P3OUTCR. Port P3 has a separate data input register. The output latch state can be read from the P3DR register, and the pin state can be read from the P3PRD register. Table 5-6 Register Programming for Port P3 (P30 to P37) Programmed Value Function P3DR Port input, external interrupt input, timer/counter input, serial interface input, UART input Port "0" output Port "1" output, serial interface output, UART output, divider output "1" "0" "1" Set as appropriate. P3OUTCR "0" STOP OUTEN P3OUTCRi P3OUTCRi input Data input (P3PRD) Output latch read (P3DR) Data output (P3DR) Control output Control input D Q P3i Note) i = 7~0 D Q Output latch Figure 5-5 Port P3 Page 59 5. I/O Ports 5.4 Port P3 (P30 to P37) TMP86CS28FG P3DR (0003H) R/W P3OUTCR (002BH) 7 P37 TC10 INT4 7 6 P36 SCK 5 P35 SI TXD1 5 4 P34 SO RXD1 4 3 P33 2 P32 1 P31 DVO 0 P30 INT0 (Initial value: 1111 1111) 6 3 2 1 0 (Initial value: 0000 0000) P3OUTCR Port P3 output circuit control (set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P3PRD (0FF3H) Read only 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 Page 60 TMP86CS28FG 5.5 Port P4 (P40 to P47) Port P4 is an 8-bit input/output port that can also be used for external interrupt input, PPG output, timer/counter input, or LCD segment output. A reset initializes the output latch (P4DR) to "1", the Pch control (P4OUTCR) to "0", and the LCD output control register (P4LCR) to "0". To use a pin in Port P4 as an input port, external interrupt input, or timer/counter input, set P4DR to "1" and then set the corresponding bit in P4LCR and P4OUTCR to "0". To use a pin in Port P4 as an LCD segment output, set the corresponding bit in P4LCR to "1". To use a pin in Port P4 as a PPG output, set P4DR to "1" and then set the corresponding bit in P4LCR to "0". The output circuit of Port P4 can be set either as sink open-drain outut ("0") or CMOS output ("1") individually for each bit in P4OUTCR. Port P4 has a separate data input register. The output latch state can be read from the P4DR register, and the pin state can be read from the P4PRD register. Table 5-7 Register Programming for Port P4 (P40 to P47) Programmed Value Function P4DR Port input, external interrupt input, timer/counter input Port "0" output Port "1" output PPG output LCD segment output "1" "0" "1" "1" * * Set as appropriate. P4OUTCR "0" P4LCR "0" "0" "0" "0" "1" Note: An asterisk (*) indicates that either "1" or "0" can be set. STOP OUTEN P4OUTCRi P4OUTCRi input P4LCRi input P4LCRi Data input (P4PRD) Output latch read (P4DR) Data output (P4DR) Control output Control input D Q P4i Note) i = 7~0 D Q D Q Output latch LCD data output Figure 5-6 Port P4 Page 61 5. I/O Ports 5.5 Port P4 (P40 to P47) TMP86CS28FG 7 P4DR (0004H) R/W P47 SEG32 6 P46 SEG31 5 P45 SEG30 4 P44 SEG29 3 P43 SEG28 TC11 2 P42 SEG27 PPG1 1 P41 SEG26 INT2 0 P40 SEG25 INT1 (Initial value: 0000 0000) P4LCR (0FD4H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P4LCR Port P4 segment output control (Set for each bit individually) 0: Input/output port 1: LCD segment output R/W P4OUTCR (0FFBH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P4OUTCR P4 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P4PRD (0FF4H) Read only 7 P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 Page 62 TMP86CS28FG 5.6 Port P5 (P50 to P57) Port P5 is an 8-bit input/output port that can also be used for timer/counter input/output, LCD segment output, or UART input/output. A reset initializes the output latch (P5DR) to "1", the Pch control (P5OUTCR) to "0", and the LCD output control register (P5LCR) to "0". To use a pin in Port P5 as an input port, timer/counter input, or UART input, set P5DR to "1" and then set the corresponding bit in P5LCR and P5OUTCR to "0". To use a pin in Port P5 as an LCD segment output, set the corresponding bit in P5LCR to "1". To use a pin in Port P5 as a UART output or timer/counter output, set P5DR to "1" and then set the corresponding bit in P5LCR to "0". The output circuit of Port P5 can be set either as sink open-drain output ("0") or CMOS otuput ("1") individually for each bit in P5OUTCR. Port P5 has a separate data input register. The output latch state can be read from the P5DR register, and the pin state can be read from the P5PRD register. Table 5-8 Register Programming for Port P5 (P50 to P57) Programmed Value Function P5DR Port input, UART input, timer/counter input Port "0" output Port "1" output, UART output LCD segment output "1" "0" "1" * P5OUTCR "0" Set as appropriate. * P5LCR "0" "0" "0" "1" Note: An asterisk (*) indicates that either "1" or "0" can be set. STOP OUTEN P5OUTCRi P5OUTCRi input P5LCRi input P5LCRi Data input (P5PRD) Output latch read (P5DR) Data output (P5DR) Control output Control input D Q P5i Note) i = 7~0 D Q D Q Output latch LCD data output Figure 5-7 Port P5 Page 63 5. I/O Ports 5.6 Port P5 (P50 to P57) TMP86CS28FG 7 P5DR (0005H) R/W P57 SEG24 6 P56 SEG25 5 P55 SEG26 TC6 PWM6 PDO6 4 P54 SEG27 TC5 PWM5 PDO5 3 P53 SEG28 TC4 PWM4 PDO4 2 P52 SEG29 TC3 PWM3 PDO3 1 P51 SEG30 RXD0 0 P50 SEG31 TXD0 (Initial value: 0000 0000) P5LCR (0FD5H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P5LCR Port P5 segment output control (Set for each bit individually) 0: Input/output port 1: LCD segment output R/W P5OUTCR (0FFCH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P5OUTCR Port P5 input/output control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P5PRD (0FF5H) Read only 7 P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Page 64 TMP86CS28FG 5.7 Port P6 (P60 to P67) Port P6 is an 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P6DR) to "1", the Pch control (P6OUTCR) to "0", and the LCD output control register (P6LCR) to "0". To use a pin in Port P6 as an input port, set P6DR to "1" and then set the corresponding bit in P6LCR and P6OUTCR to "0". To use a pin in Port P6 as an LCD segment output, set the corresponding bit in P6LCR to "1". The output circuit of Port P6 can be set either as sink open-drain output ("0") or CMOS output ("1") individually for each bit in P6OUTCR. Port P6 has a separate data input register. The outut latch state can be read from the P6DR register, and the pin state can be read from the P6PRD register. Table 5-9 Register Programming for Port P6 (P60 to P67) Programmed Value Function P6DR Port input Port "0" output Port "1" output LCD segment output "1" "0" "1" * P6OUTCR "0" Set as appropriate. * P6LCR "0" "0" "0" "1" Note: An asterisk (*) indicates that either "1" or "0" can be set. STOP OUTEN P6OUTCRi P6OUTCRi input P6LCRi input P6LCRi Data input (P6PRD) Output latch read (P6DR) Data output (P6DR) D Q P6i Note) i = 7~0 D Q D Q Output latch LCD data output Figure 5-8 Port P6 Page 65 5. I/O Ports 5.7 Port P6 (P60 to P67) TMP86CS28FG P6DR (0006H) R/W P6LCR (0FD6H) 7 P67 SEG16 7 6 P66 SEG17 6 5 P65 SEG18 5 4 P64 SEG19 4 3 P63 SEG20 3 2 P62 SEG21 2 1 P61 SEG22 1 0 P60 SEG23 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P6LCR Port P6 segment output control (Set for each bit individually) 0: Input/output port 1: Segment output R/W P6OUTCR (0FFDH) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P6CR2 Port P6 input/output control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P6PRD (0FF6H) Read only 7 P67 6 P66 5 P65 4 P64 3 P63 2 P62 1 P61 0 P60 Page 66 TMP86CS28FG 5.8 Port P7 (P70 to P77) Port P7 is an 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P7DR) to "1", the Pch control (P7OUTCR) to "0", and the LCD output control register (P7LCR) to "0". To use a pin in Port P7 as an input port, set P7DR to "1" and then set the corresponding bit in P7LCR and P7OUTCR to "0". To use a pin in Port P7 as an LCD segment output, set the corresponding bit in P7LCR to "1". The output circuit of Port P7 can be set either as sink open-drain output ("0") or CMOS output ("1") individually for each bit in P7OUTCR. Port P7 has a separate data input register. The output latch state can be read from the P7DR register, and the pin state can be read from the P7PRD register. Table 5-10 Register Programming for Port P7 (P70 to P77) Programmed Value Function P7DR Port input Port "0" output Port "1" output LCD segment output "1" "0" "1" * P7OUTCR "0" Set as appropriate. * P7LCR "0" "0" "0" "1" Note: An asterisk (*) indicates that either "1" or "0" can be set. STOP OUTEN P7OUTCRi P7OUTCRi input P7LCRi input P7LCRi Data input (P7PRD) Output latch read (P7DR) Data output (P7DR) LCD data output D Q P7i Note) i = 7~0 D Q D Q Output latch Figure 5-9 Port P7 Page 67 5. I/O Ports 5.8 Port P7 (P70 to P77) TMP86CS28FG P7DR (0007H) R/W P7LCR (0FD7H) 7 P77 SEG8 7 6 P76 SEG9 6 5 P75 SEG10 5 4 P74 SEG11 4 3 P73 SEG12 3 2 P72 SEG13 2 1 P71 SEG14 1 0 P70 SEG15 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P7LCR Port P7 segment output control (set for each bit individually) 0: Input/output port 1: Segment output R/W P7OUTCR (0FFEH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P7OUTCR Port P7 input/output control (set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P7PRD (0FF7H) Read only 7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70 Page 68 TMP86CS28FG 5.9 Port P8 (P80 to P87) Port P8 is an 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P8DR) to "1", the Pch control (P8OUTCR) to "0", and the LCD output control register (P8LCR) to "0". To use a pin in Port P8 as an input port, set P8DR to "1" and then set the corresponding bit in P8LCR and P8OUTCR to "0". To use a pin in Port P8 as an LCD segment output, set the corresponding bit in P8LCR to "1". The output circuit of Port P8 can be set either as sink open-drain output ("0") or CMOS output ("1") individually for each bit in P8OUTCR. Port P8 has a separate data input register. The output latch state can be read from the P8DR register, and the pin state can be read from the P8PRD register. Table 5-11 Register Programming for Port P8 (P80 to P87) Port Input Function P8DR Port input Port "0" output Port "1" output LCD segment output "1" "0" "1" * P8OUTCR "0" Set as appropriate. * P8LCR "0" "0" "0" "1" Note: An asterisk (*) indicates that either "1" or "0" can be set. STOP OUTEN P8OUTCRi P8OUTCRi input P8LCRi input P8LCRi Data input (P8PRD) Output latch read (P8DR) Data output (P8DR) LCD data output D Q P8i Note) i = 7~0 D Q D Q Output latch Figure 5-10 Port P8 Page 69 5. I/O Ports 5.9 Port P8 (P80 to P87) TMP86CS28FG P8DR (0008H) R/W P8LCR (0FD8H) 7 P87 SEG0 7 6 P86 SEG1 6 5 P85 SEG2 5 4 P84 SEG3 4 3 P83 SEG4 3 2 P82 SEG5 2 1 P81 SEG6 1 0 P80 SEG7 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P8LCR Port P8 segment output control (Set for each bit individually) 0: Input/output port 1: LCD segment output R/W P8OUTCR (0FFFH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P8OUTCR Port P8 input/output control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output R/W P8PRD (0FF8H) Read only 7 P87 6 P86 5 P85 4 P84 3 P83 2 P82 1 P81 0 P80 Page 70 TMP86CS28FG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 6-1 Watchdog Timer Configuration Page 71 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86CS28FG 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 72 TMP86CS28FG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "6.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 6.2.2 Watchdog Timer Enable Setting WDTCR1 Page 73 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86CS28FG 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary counter : WDTEN 0, WDTCR2 Disable code Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 6.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 083FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 74 TMP86CS28FG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 6-2 Watchdog Timer Interrupt Page 75 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86CS28FG 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select operation at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is required) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 6.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 6.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 6.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 76 TMP86CS28FG 6.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 77 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86CS28FG Page 78 TMP86CS28FG 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 7-1 Time Base Timer configuration 7.1.2 Control Time Base Timer is controlled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 79 7. Time Base Timer (TBT) 7.1 Time Base Timer TMP86CS28FG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 7.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 7-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 7-2 Time Base Timer Interrupt Page 80 TMP86CS28FG 7.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 7.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 7-3 Divider Output 7.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 81 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) TMP86CS28FG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 82 8.1 8.1.1 MCAP10 S INTTC10 interript A TC10S Configuration Y B Start MPPG10 TC10S clear Clear PPG output mode 2 Decoder Set Q Command start Pulse width measurement mode External trigger External trigger start Rising Falling 16-Bit TimerCounter 10 Edge detector METT10 TC1 Clear B A S Match CMP Y Source clock 16-bit up-counter Pulse width measurement mode Port (Note) D 8. 16-Bit TimerCounter (TC10,TC11) Figure 8-1 TimerCounter 10 (TC10) Page 83 Clear Selector Set Capture TC10DRB TC10DRA 16-bit timer register A, B Toggle Enable S Q PPG output mode Internal reset Write to TC10CR fc/211, fs/23 A fc/27 B Y fc/23 C S Toggle Q Set Clear Port (Note) pin 2 Window mode TC10CK ACAP10 TC10CR TFF10 TC10 control register Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". TMP86CS28FG 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG 8.1.2 TimerCounter Control The TimerCounter 10 is controlled by the TimerCounter 10 control register (TC10CR) and two 16-bit timer registers (TC10DRA and TC10DRB). Timer Register 15 TC10DRA (0011H, 0010H) TC10DRB (0013H, 0012H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC10DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC10DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC10DRAL (0010H) Read/Write TC10DRBL (0012H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 10 Control Register 7 TC10CR (0014H) 6 ACAP10 MCAP10 METT10 MPPG10 5 4 3 2 1 0 Read/Write (Initial value: 0000 0000) TFF10 TC10S TC10CK TC10M TFF10 ACAP10 MCAP10 METT10 MPPG10 Timer F/F10 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC10S TC10 start control - O O O O O R/W - O O O O O NORMAL1/2, IDLE1/2 mode DV7CK = 0 TC10CK TC10 source clock select [Hz] 00 01 10 11 TC10 operating mode select fc/211 fc/27 fc/23 DV7CK = 1 fs/23 fc/27 fc/23 External clock (TC10 pin input) Divider SLOW, SLEEP mode fs/23 - - R/W DV9 DV5 DV1 TC10M 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC10DRAH and TC10DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC10DRAL and TC10DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC10CR1 during TC10S=00. Set the timer F/F10 control until the first timer start after setting the PPG mode. Page 84 TMP86CS28FG Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC10DRA > TC10DRB > 1 (PPG output mode), TC10DRA > 1 (other modes) Note 6: Set TFF10 to "0" in the mode except PPG output mode. Note 7: Set TC10DRB after setting TC10M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC10S) is cleared to "00" automatically, and the timer stops. After the STOP mode is exited, set the TC10S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC10. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC10DRB by the source clock of up-counter after setting TC10CR 8.1.3 Function TimerCounter 10 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.1.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC10DRA) value is detected, an INTTC10 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC10CR NORMAL1/2, IDLE1/2 mode TC10CK DV7CK = 0 Resolution [s] 00 01 10 128 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m Resolution [s] 244.14 8.0 0.5 DV7CK = 1 Maximum Time Setting [s] 16.0 0.524 32.77 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - SLOW, SLEEP mode Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC10CR), 00000000B (TC10CR), 00010000B (EIRL). 7 (TC10DRA), 1E84H ; Sets the timer register (1 s / 211/fc = 1E84H) ; IMF= "0" ; Enables INTTC10 ; IMF= "1" ; Selects the source clock and mode ; Starts TC10 Page 85 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG Example 2 :Auto-capture LD : LD (TC10CR), 01010000B : WA, (TC10DRB) ; Reads the capture value ; ACAP10 1 Note: Since the up-counter value is captured into TC10DRB by the source clock of up-counter after setting TC10CR Timer start Source clock Counter TC10DRA 0 ? 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 n INTTC10 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture TC10DRB ? m-1 m m+1 m+2 n-1 Capture n n+1 ACAP10 (b) Auto-capture Figure 8-2 Timer Mode Timing Chart Page 86 TMP86CS28FG 8.1.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC10 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC10CR Since the TC10 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC10 pin (fc =16 MHz) LDW DI SET EI LD LD (TC10CR), 00000100B (TC10CR), 00100100B (EIRL). 7 (TC10DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC10 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC10 external trigger, METT10 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC10 pin (fc =16 MHz) LDW DI SET EI LD LD (TC10CR), 00000100B (TC10CR), 01110100B (EIRL). 7 (TC10DRA), 01F4H ; 4 ms / 27/fc = 1F4H ; IMF= "0" ; Enables INTTC10 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC10 external trigger, METT10 = 0 Page 87 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG Count start TC10 pin input Count start At the rising edge (TC10S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC10DRA n Match detect Count clear INTTC10 interrupt request (a) Trigger start (METT10 = 0) At the rising edge (TC10S = 10) Count start TC10 pin input Count clear Count start Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC10DRA n Match detect Count clear INTTC10 interrupt request Note: m < n (b) Trigger start and stop (METT10 = 1) Figure 8-3 External Trigger Timer Mode Timing Chart Page 88 TMP86CS28FG 8.1.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC10 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC10CR Timer start TC10 pin Input Up-counter TC10DRA INTTC10 interrput request ? n-1 0 1 2 n 0 1 2 At the rising edge (TC10S = 10) n Match detect Counter clear Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulse Width to TC10 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode High-going Low-going 23/fc 23/fc SLOW1/2, SLEEP1/2 Mode 23/fs 23/fs Page 89 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG 8.1.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC10 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC10DRA value is detected, an INTTC10 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC10CR Count start Timer start Count stop Count start TC10 pin input Internal clock Counter TC10DRA INTTC10 interrput request ? 7 Match detect (a) Positive logic (TC10S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC10 pin input Internal clock Counter TC10DRA INTTC10 interrput request (b) Negative logic (TC10S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-5 Window Mode Timing Chart Page 90 TMP86CS28FG 8.1.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC10 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC10CR Note 1: The captured value must be read from TC10DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC10DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 91 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG Example :Duty measurement (resolution fc/27 [Hz]) CLR LD DI SET EI LD : PINTTC10: CPL JRS LD LD LD RETI SINTTC10: LD LD LD : RETI : VINTTC10: DW PINTTC10 ; INTTC10 Interrupt vector ; Duty calculation A, (TC10DRBL) W,(TC10DRBH) (WIDTH), WA ; Stores cycle in RAM ; Reads TC10DRB (Cycle) (INTTC10SW). 0 F, SINTTC10 A, (TC10DRBL) W,(TC10DRBH) (HPULSE), WA ; Stores high-level pulse width in RAM ; Reads TC10DRB (High-level pulse width) ; INTTC10 interrupt, inverts and tests INTTC10 service switch (TC10CR), 00100110B (EIRL). 7 (INTTC10SW). 0 (TC10CR), 00000110B ; INTTC10 service switch initial setting Address set to convert INTTC10SW at each INTTC10 ; Sets the TC10 mode and source clock ; IMF= "0" ; Enables INTTC10 ; IMF= "1" ; Starts TC10 with an external trigger at MCAP10 = 0 WIDTH HPULSE TC10 pin INTTC10 interrupt request INTTC10SW Page 92 TMP86CS28FG Count start TC10 pin input Trigger Count start (TC10S = "10") Internal clock Counter TC10DRB INTTC10 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP10 = "1") Count start Count start (TC10S = "10") TC10 pin input Internal clock Counter TC10DRB INTTC10 interrupt request [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP10 = "0") 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 Figure 8-6 Pulse Width Measurement Mode Page 93 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG 8.1.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC10CR Since the output level of the PPG pin can be set with TC10CR Note 1: To change TC10DRA or TC10DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC10CR Page 94 TMP86CS28FG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 MHz) Setting port LD LDW LDW LD (TC10CR), 10000111B (TC10DRA), 007DH (TC10DRB), 0019H (TC10CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc ms = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD LDW LDW LD : LD LD LD LD (TC10CR), 10000111B (TC10DRA), 007DH (TC10DRB), 0019H (TC10CR), 10010111B : (TC10CR), 10000111B (TC10CR), 10000100B (TC10CR), 00000111B (TC10CR), 00010111B ; Stops the timer ; Sets the timer mode ; Sets the PPG mode, TFF10 = 0 ; Starts the timer ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc s = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer I/O port output latch shared with PPG output Data output D R Q Port output enable PPG pin Function output TC10CR Figure 8-7 PPG Output Page 95 8. 16-Bit TimerCounter (TC10,TC11) 8.1 16-Bit TimerCounter 10 TMP86CS28FG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC10DRB n Match detect TC10DRA m PPG pin output INTTC10 interrupt request Note: m > n (a) Continuous pulse generation (TC10S = 01) Count start TC10 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC10DRB n TC10DRA m PPG pin output INTTC10 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC10S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 96 8.2 8.2.1 MCAP11 S INTTC11 interript Configuration A TC11S Y B Command start Start MPPG11 TC11S clear Clear METT11 PPG output mode Set Q 2 Decoder Pulse width measurement mode External trigger External trigger start Rising Falling 16-Bit TimerCounter 11 Edge detector TC1 Clear B A S Match CMP Window mode Clear Selector S Q Set Capture TC11DRB TC11DRA ACAP11 16-bit timer register A, B Enable Toggle Y Source clock 16-bit up-counter Pulse width measurement mode Port (Note) D Figure 8-9 TimerCounter 11 (TC11) Page 97 Write to TC11CR fc/2 11, fs/2 3 A fc/2 7 B Y fc/23 C S Toggle Q Set Clear Port (Note) PPG output mode Internal reset pin 2 TC11CK TC11CR TFF11 TC11 control register Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". TMP86CS28FG 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG 8.2.2 TimerCounter Control The TimerCounter 11 is controlled by the TimerCounter 11 control register (TC11CR) and two 16-bit timer registers (TC11DRA and TC11DRB). Timer Register 15 TC11DRA (0021H, 0020H) TC11DRB (0023H, 0022H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC11DRAH (0021H) (Initial value: 1111 1111 1111 1111) TC11DRBH (0023H) (Initial value: 1111 1111 1111 1111) TC11DRAL (0020H) Read/Write TC11DRBL (0022H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 11 Control Register 7 TC11CR (0024H) 6 ACAP11 MCAP11 METT11 MPPG11 5 4 3 2 1 0 Read/Write (Initial value: 0000 0000) TFF11 TC11S TC11CK TC11M TFF11 ACAP11 MCAP11 METT11 MPPG11 Timer F/F11 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC11S TC11 start control - O O O O O R/W - O O O O O NORMAL1/2, IDLE1/2 mode DV7CK = 0 TC11CK TC11 source clock select [Hz] 00 01 10 11 TC11 operating mode select fc/211 fc/27 fc/23 DV7CK = 1 fs/23 fc/27 fc/23 External clock (TC11 pin input) Divider SLOW, SLEEP mode fs/23 - - R/W DV9 DV5 DV1 TC11M 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC11DRAH and TC11DRBH) is written. Therefore, write the lower Page 98 TMP86CS28FG byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC11DRAL and TC11DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC11CR1 during TC11S=00. Set the timer F/F10 control until the first timer start after setting the PPG mode. Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC11DRA > TC11DRB > 1 (PPG output mode), TC11DRA > 1 (other modes) Note 6: Set TFF11 to "0" in the mode except PPG output mode. Note 7: Set TC11DRB after setting TC11M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC11S) is cleared to "00" automatically, and the timer stops. After the STOP mode is exited, set the TC11S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC11. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC11DRB by the source clock of up-counter after setting TC11CR 8.2.3 Function TimerCounter 11 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.2.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC11DRA) value is detected, an INTTC11 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC11CR NORMAL1/2, IDLE1/2 mode TC11CK DV7CK = 0 Resolution [s] 00 01 10 128 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m Resolution [s] 244.14 8.0 0.5 DV7CK = 1 Maximum Time Setting [s] 16.0 0.524 32.77 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - SLOW, SLEEP mode Page 99 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC11CR), 00000000B (TC11CR), 00010000B (EIRL). 2 (TC11DRA), 1E84H ; Sets the timer register (1 s / 211/fc = 1E84H) ; IMF= "0" ; Enables INTTC11 ; IMF= "1" ; Selects the source clock and mode ; Starts TC11 Example 2 :Auto-capture LD : LD (TC11CR), 01010000B : WA, (TC11DRB) ; Reads the capture value ; ACAP11 1 Note: Since the up-counter value is captured into TC11DRB by the source clock of up-counter after setting TC11CR Timer start Source clock Counter TC11DRA 0 ? 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 n INTTC11 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture TC11DRB ? m-1 m m+1 m+2 n-1 Capture n n+1 ACAP11 (b) Auto-capture Figure 8-10 Timer Mode Timing Chart Page 100 TMP86CS28FG 8.2.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC11 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC11CR Since the TC11 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC11 pin (fc =16 MHz) LDW DI SET EI LD LD (TC11CR), 00000100B (TC11CR), 00100100B (EIRL). 2 (TC11DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC11 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC11 external trigger, METT11 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC11 pin (fc =16 MHz) LDW DI SET EI LD LD (TC11CR), 00000100B (TC11CR), 01110100B (EIRL). 2 (TC11DRA), 01F4H ; 4 ms / 27/fc = 1F4H ; IMF= "0" ; Enables INTTC11 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC11 external trigger, METT11 = 0 Page 101 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG Count start TC11 pin input Count start At the rising edge (TC11S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC11DRA n Match detect Count clear INTTC11 interrupt request (a) Trigger start (METT11 = 0) At the rising edge (TC11S = 10) Count start TC11 pin input Count clear Count start Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC11DRA n Match detect Count clear INTTC11 interrupt request Note: m < n (b) Trigger start and stop (METT11 = 1) Figure 8-11 External Trigger Timer Mode Timing Chart Page 102 TMP86CS28FG 8.2.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC11 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC11CR Timer start TC11 pin Input Up-counter TC11DRA INTTC11 interrput request ? n-1 0 1 2 n 0 1 2 At the rising edge (TC11S = 10) n Match detect Counter clear Figure 8-12 Event Counter Mode Timing Chart Table 8-4 Input Pulse Width to TC11 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode High-going Low-going 23/fc 23/fc SLOW1/2, SLEEP1/2 Mode 23/fs 23/fs Page 103 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG 8.2.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC11 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC11DRA value is detected, an INTTC11 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC11CR Count start Timer start Count stop Count start TC11 pin input Internal clock Counter TC11DRA INTTC11 interrput request ? 7 Match detect (a) Positive logic (TC11S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC11 pin input Internal clock Counter TC11DRA INTTC11 interrput request (b) Negative logic (TC11S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-13 Window Mode Timing Chart Page 104 TMP86CS28FG 8.2.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC11 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC11CR Note 1: The captured value must be read from TC11DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC11DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 105 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG Example :Duty measurement (resolution fc/27 [Hz]) CLR LD DI SET EI LD : PINTTC11: CPL JRS LD LD LD RETI SINTTC11: LD LD LD : RETI : VINTTC11: DW PINTTC11 ; INTTC11 Interrupt vector ; Duty calculation A, (TC11DRBL) W,(TC11DRBH) (WIDTH), WA ; Stores cycle in RAM ; Reads TC11DRB (Cycle) (INTTC11SW). 0 F, SINTTC11 A, (TC11DRBL) W,(TC11DRBH) (HPULSE), WA ; Stores high-level pulse width in RAM ; Reads TC11DRB (High-level pulse width) ; INTTC11 interrupt, inverts and tests INTTC11 service switch (TC11CR), 00100110B (EIRH). 7 (INTTC11SW). 0 (TC11CR), 00000110B ; INTTC11 service switch initial setting Address set to convert INTTC11SW at each INTTC11 ; Sets the TC11 mode and source clock ; IMF= "0" ; Enables INTTC11 ; IMF= "1" ; Starts TC11 with an external trigger at MCAP11 = 0 WIDTH HPULSE TC11 pin INTTC11 interrupt request INTTC11SW Page 106 TMP86CS28FG Count start TC11 pin input Trigger Count start (TC11S = "10") Internal clock Counter TC11DRB INTTC11 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP11 = "1") Count start Count start (TC11S = "10") TC11 pin input Internal clock Counter TC11DRB INTTC11 interrupt request [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP11 = "0") 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 Figure 8-14 Pulse Width Measurement Mode Page 107 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG 8.2.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC11CR Since the output level of the PPG pin can be set with TC11CR Note 1: To change TC11DRA or TC11DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC11CR Page 108 TMP86CS28FG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 MHz) Setting port LD LDW LDW LD (TC11CR), 10000111B (TC11DRA), 007DH (TC11DRB), 0019H (TC11CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc ms = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD LDW LDW LD : LD LD LD LD (TC11CR), 10000111B (TC11DRA), 007DH (TC11DRB), 0019H (TC11CR), 10010111B : (TC11CR), 10000111B (TC11CR), 10000100B (TC11CR), 00000111B (TC11CR), 00010111B ; Stops the timer ; Sets the timer mode ; Sets the PPG mode, TFF11 = 0 ; Starts the timer ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc s = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer I/O port output latch shared with PPG output Data output D R Q Port output enable PPG pin Function output TC11CR Figure 8-15 PPG Output Page 109 8. 16-Bit TimerCounter (TC10,TC11) 8.2 16-Bit TimerCounter 11 TMP86CS28FG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC11DRB n Match detect TC11DRA m PPG pin output INTTC11 interrupt request Note: m > n (a) Continuous pulse generation (TC11S = 01) Count start TC11 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC11DRB n TC11DRA m PPG pin output INTTC11 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC11S = 10) Note: m > n Figure 8-16 PPG Mode Timing Chart Page 110 TMP86CS28FG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 9-1 8-Bit TimerCounter 3, 4 Page 111 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (0015H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (0019H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (0009H) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 112 TMP86CS28FG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 113 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (0016H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (001AH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (000AH) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC3 overflow signal regardless of the TC4CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 114 TMP86CS28FG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 115 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 116 TMP86CS28FG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Maximum Time Setting fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating clock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRE). 5 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 117 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4) 9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 118 TMP86CS28FG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 119 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 120 Counter 0 1 2 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86CS28FG TMP86CS28FG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 9-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 121 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 PWREG4 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 122 n One cycle period m Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86CS28FG TMP86CS28FG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Maximum Time Setting fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating clock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRE). 5 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 123 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR 4 Note 1: In the event counter mode, fix TCjCR 9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 124 TMP86CS28FG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 9-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2s 8.2 ms 4.1 ms fs = 32.768 kHz 16 s - - - 2s - - Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 125 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 126 b Shift Shift bm Match detect an One cycle period bm PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an cp INTTC4 interrupt request TMP86CS28FG TMP86CS28FG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/ 2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 127 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 128 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86CS28FG TMP86CS28FG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 9.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Minimum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 129 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CS28FG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time Setting (TTREG4, 3 = 0100H) 16 s Maximum time Setting (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 130 TMP86CS28FG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC6 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC6 pin TC6M TC6S TFF6 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC6S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F6 PDO6/PWM6/ PPG6 pin TC6CK TC6CR TTREG6 PWREG6 PWM, PPG mode DecodeEN TFF6 PDO, PWM, PPG mode 16-bit mode TC5S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC5 pin TC5M TC5S TFF5 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC5 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F5 PDO5/PWM5/ pin TC5CK TC5CR TTREG5 PWREG5 PWM mode DecodeEN TFF5 PDO, PWM mode 16-bit mode Figure 10-1 8-Bit TimerCounter 5, 6 Page 131 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CS28FG 10.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (0017H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG5 (001BH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG5) setting while the timer is running. Note 2: Do not change the timer register (PWREG5) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 5 Control Register TC5CR (000BH) 7 TFF5 6 5 TC5CK 4 3 TC5S 2 1 TC5M 0 (Initial value: 0000 0000) TFF5 Time F/F5 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC5CK Operating clock selection [Hz] 010 011 100 101 110 111 TC5S TC5 start control 0: 1: 000: 001: TC5M TC5M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC6M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC5M, TC5CK and TFF5 settings while the timer is running. Note 3: To stop the timer operation (TC5S= 1 0), do not change the TC5M, TC5CK and TFF5 settings. To start the timer operation (TC5S= 0 1), TC5M, TC5CK and TFF5 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR Page 132 TMP86CS28FG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 103. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 133 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CS28FG The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (0018H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG6 (001CH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running. Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 6 Control Register TC6CR (000CH) 7 TFF6 6 5 TC6CK 4 3 TC6S 2 1 TC6M 0 (Initial value: 0000 0000) TFF6 Timer F/F6 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC6 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC6CK Operating clock selection [Hz] 010 011 100 101 110 111 TC6S TC6 start control 0: 1: 000: 001: 010: TC6M TC6M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC6M, TC6CK and TFF6 settings while the timer is running. Note 3: To stop the timer operation (TC6S= 1 0), do not change the TC6M, TC6CK and TFF6 settings. To start the timer operation (TC6S= 0 1), TC6M, TC6CK and TFF6 can be programmed. Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC5 overflow signal regardless of the TC6CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR Page 134 TMP86CS28FG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR Table 10-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - TC6 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note 2: : Available source clock Table 10-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - TC6 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note2: : Available source clock Page 135 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CS28FG Table 10-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG6, 5) 65535 256 (TTREG6, 5) 65535 2 (PWREG6, 5) 65534 1 (PWREG6, 5) < (TTREG6, 5) 65535 16-bit PPG and (PWREG6, 5) + 1 < (TTREG6, 5) Register Value Note: n = 5 to 6 Page 136 TMP86CS28FG 10.3 Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 10.3.1 8-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 10-4 Source Clock for TimerCounter 5, 6 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Maximum Time Setting fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter6, fc = 16.0 MHz) LD DI SET EI LD LD (TC6CR), 00010000B (TC6CR), 00011000B : Sets the operating clock to fc/27, and 8-bit timer mode. : Starts TC6. (EIRD). 0 : Enables INTTC6 interrupt. (TTREG6), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 137 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CS28FG TC6CR Internal Source Clock Counter TTREG6 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC6) 10.3.2 8-Bit Event Counter Mode (TC5, 6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC6CR Counter TTREG6 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-3 8-Bit Event Counter Mode Timing Chart (TC6) 10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 138 TMP86CS28FG Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port LD LD LD (TTREG6), 3DH (TC6CR), 00010001B (TC6CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC6. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 139 10.1 Configuration 10. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 10-4 8-Bit PDO Mode Timing Chart (TC6) Match detect Match detect Match detect Page 140 Counter 0 1 2 TTREG6 ? n Match detect Timer F/F6 Set F/F PDO6 pin INTTC6 interrupt request Held at the level when the timer is stopped TMP86CS28FG TMP86CS28FG 10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 10-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 141 10.1 Configuration 10. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Internal source clock n Write to PWREG6 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG6 PWREG6 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 10-5 8-Bit PWM Mode Timing Chart (TC6) Page 142 n One cycle period m Shift Shift registar ? n Match detect Timer F/F6 PWM6 pin n p INTTC6 interrupt request TMP86CS28FG TMP86CS28FG 10.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR Note 1: In the timer mode, fix TCjCR Table 10-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Maximum Time Setting fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC5CR), 13H :Sets the operating clock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRD). 0 : Enables INTTC6 interrupt. (TTREG5), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC6CR), 04H (TC6CR), 0CH TC6CR Internal source clock Counter TTREG5 (Lower byte) TTREG6 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-6 16-Bit Timer Mode Timing Chart (TC5 and TC6) Page 143 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CS28FG 10.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR 4 Note 1: In the event counter mode, fix TCjCR 10.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC6 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F6 by TC6CR Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR Page 144 TMP86CS28FG CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the PWM6 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM6 pin during the warm-up period time after exiting the STOP mode. Table 10-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2s 8.2 ms 4.1 ms fs = 32.768 kHz 16 s - - - 2s - - Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG5), 07D0H (TC5CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC6CR), 056H (TC6CR), 05EH Page 145 10.1 Configuration 10. 8-Bit TimerCounter (TC5, TC6) TC6CR |